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half_adder.vhd — Challenge #42

✓ Accepted

-- Half Adder in VHDL
entity half_adder is
  port (
    A, B : in  std_logic;
    S, C : out std_logic
  );
end half_adder;

architecture rtl of half_adder is
begin
  S <= A xor B;
  C <= A and B;
end rtl;

Runtime

12 ms

Test cases

8 / 8 passed

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-- D Flip-Flop
process(clk)
if rising_edge(clk) then
Q <= D;
end if;
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Topics

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Logic Gates

AND, OR, NOT, NAND, NOR, XOR fundamentals

48 challenges

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36 challenges

35%

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30 challenges

70%

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85%

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22 challenges

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Expert Digital DesignThrough Practice

Everything you need to master digital design

Write real HDL code

Test your theory knowledge

Draw and simulate circuits

From zero to confident in 4 steps

Pick a challenge

Design or answer

Get instant feedback

Track your progress

From gates to processors

Trusted by 12,000+ learners

Simple, transparent pricing

Ready to level up yourdigital design skills?

Ready to level up your
digital design skills?